/*
 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
 * 
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 #include "ddr_core.h"
 #include "asm/arch/socregs.h"
 #include "config.h"
 #define PRIMARY_CPU  0

#ifdef CONFIG_L2C_AS_RAM
	.section section_mmu_table
mmu_table1:
	.word	0x00004c0a
	.word	0x00104c0a
	.word	0x00204c0a
	.word	0x00304c0a
	.word	0x00404c0a
	.word	0x00504c0a
	.word	0x00604c0a
	.word	0x00704c0a
	.word	0x00804c0a
	.word	0x00904c0a
	.word	0x00a04c0a
	.word	0x00b04c0a
	.word	0x00c04c0a
	.word	0x00d04c0a
	.word	0x00e04c0a
	.word	0x00f04c0a
	.word	0x01004c06 @DDR_SHMOO_RELATED_CHANGE: make 16MB-32MB area as L1 cacheable write-back mode requested by shmoo memory test
	.word	0x01104c06 
	.word	0x01204c06 
	.word	0x01304c06
	.word	0x01404c06
	.word	0x01504c06
	.word	0x01604c06
	.word	0x01704c06
	.word	0x01804c06
	.word	0x01904c06
	.word	0x01a04c06
	.word	0x01b04c06
	.word	0x01c04c06
	.word	0x01d04c06
	.word	0x01e04c06
	.word	0x01f04c06 
	.word	0x02005c06 @DDR_SHMOO_RELATED_CHANGE: make 32MB-128MB area as L1&L2 cacheable write-back mode requested by stress memory test
	.word	0x02105c06 
	.word	0x02205c06 
	.word	0x02305c06 
	.word	0x02405c06
	.word	0x02505c06
	.word	0x02605c06
	.word	0x02705c06
	.word	0x02805c06
	.word	0x02905c06
	.word	0x02a05c06
	.word	0x02b05c06
	.word	0x02c05c06
	.word	0x02d05c06
	.word	0x02e05c06
	.word	0x02f05c06
	.word	0x03005c06
	.word	0x03105c06
	.word	0x03205c06
	.word	0x03305c06
	.word	0x03405c06
	.word	0x03505c06
	.word	0x03605c06
	.word	0x03705c06
	.word	0x03805c06
	.word	0x03905c06
	.word	0x03a05c06
	.word	0x03b05c06
	.word	0x03c05c06
	.word	0x03d05c06
	.word	0x03e05c06
	.word	0x03f05c06
	.word	0x04005c06
	.word	0x04105c06
	.word	0x04205c06
	.word	0x04305c06
	.word	0x04405c06
	.word	0x04505c06
	.word	0x04605c06
	.word	0x04705c06
	.word	0x04805c06
	.word	0x04905c06
	.word	0x04a05c06
	.word	0x04b05c06
	.word	0x04c05c06
	.word	0x04d05c06
	.word	0x04e05c06
	.word	0x04f05c06
	.word	0x05005c06
	.word	0x05105c06
	.word	0x05205c06
	.word	0x05305c06
	.word	0x05405c06
	.word	0x05505c06
	.word	0x05605c06
	.word	0x05705c06
	.word	0x05805c06
	.word	0x05905c06
	.word	0x05a05c06
	.word	0x05b05c06
	.word	0x05c05c06
	.word	0x05d05c06
	.word	0x05e05c06
	.word	0x05f05c06
	.word	0x06005c06
	.word	0x06105c06
	.word	0x06205c06
	.word	0x06305c06
	.word	0x06405c06
	.word	0x06505c06
	.word	0x06605c06
	.word	0x06705c06
	.word	0x06805c06
	.word	0x06905c06
	.word	0x06a05c06
	.word	0x06b05c06
	.word	0x06c05c06
	.word	0x06d05c06
	.word	0x06e05c06
	.word	0x06f05c06
	.word	0x07005c06
	.word	0x07105c06
	.word	0x07205c06
	.word	0x07305c06
	.word	0x07405c06
	.word	0x07505c06
	.word	0x07605c06
	.word	0x07705c06
	.word	0x07805c06
	.word	0x07905c06
	.word	0x07a05c06
	.word	0x07b05c06
	.word	0x07c05c06
	.word	0x07d05c06
	.word	0x07e05c06
	.word	0x07f05c06 @ DDR_SHMOO_RELATED_CHANGE: end of L1&L2 cacheable write-back mode
	.word	0x08002c02
	.word	0x08102c02
	.word	0x08202c02
	.word	0x08302c02
	.word	0x08402c02
	.word	0x08502c02
	.word	0x08602c02
	.word	0x08702c02
	.word	0x08802c02
	.word	0x08902c02
	.word	0x08a02c02
	.word	0x08b02c02
	.word	0x08c02c02
	.word	0x08d02c02
	.word	0x08e02c02
	.word	0x08f02c02
	.word	0x09002c02
	.word	0x09102c02
	.word	0x09202c02
	.word	0x09302c02
	.word	0x09402c02
	.word	0x09502c02
	.word	0x09602c02
	.word	0x09702c02
	.word	0x09802c02
	.word	0x09902c02
	.word	0x09a02c02
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	.word	0x09d02c02
	.word	0x09e02c02
	.word	0x09f02c02
	.word	0x0a002c02
	.word	0x0a102c02
	.word	0x0a202c02
	.word	0x0a302c02
	.word	0x0a402c02
	.word	0x0a502c02
	.word	0x0a602c02
	.word	0x0a702c02
	.word	0x0a802c02
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	.word	0x0b302c02
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	.word	0x0bd02c02
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	.word	0x0c602c02
	.word	0x0c702c02
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	.word	0x0c902c02
	.word	0x0ca02c02
	.word	0x0cb02c02
	.word	0x0cc02c02
	.word	0x0cd02c02
	.word	0x0ce02c02
	.word	0x0cf02c02
	.word	0x0d002c02
	.word	0x0d102c02
	.word	0x0d202c02
	.word	0x0d302c02
	.word	0x0d402c02
	.word	0x0d502c02
	.word	0x0d602c02
	.word	0x0d702c02
	.word	0x0d802c02
	.word	0x0d902c02
	.word	0x0da02c02
	.word	0x0db02c02
	.word	0x0dc02c02
	.word	0x0dd02c02
	.word	0x0de02c02
	.word	0x0df02c02
	.word	0x0e002c02
	.word	0x0e102c02
	.word	0x0e202c02
	.word	0x0e302c02
	.word	0x0e402c02
	.word	0x0e502c02
	.word	0x0e602c02
	.word	0x0e702c02
	.word	0x0e802c02
	.word	0x0e902c02
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	.word	0x0eb02c02
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	.word	0x0ed02c02
	.word	0x0ee02c02
	.word	0x0ef02c02
	.word	0x0f002c02
	.word	0x0f102c02
	.word	0x0f202c02
	.word	0x0f302c02
	.word	0x0f402c02
	.word	0x0f502c02
	.word	0x0f602c02
	.word	0x0f702c02
	.word	0x0f802c02
	.word	0x0f902c02
	.word	0x0fa02c02
	.word	0x0fb02c02
	.word	0x0fc02c02
	.word	0x0fd02c02
	.word	0x0fe02c02
	.word	0x0ff02c02
	.word	0x10002c02
	.word	0x10102c02
	.word	0x10202c02
	.word	0x10302c02
	.word	0x10402c02
	.word	0x10502c02
	.word	0x10602c02
	.word	0x10702c02
	.word	0x10802c02
	.word	0x10902c02
	.word	0x10a02c02
	.word	0x10b02c02
	.word	0x10c02c02
	.word	0x10d02c02
	.word	0x10e02c02
	.word	0x10f02c02
	.word	0x11002c02
	.word	0x11102c02
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	.word	0x11302c02
	.word	0x11402c02
	.word	0x11502c02
	.word	0x11602c02
	.word	0x11702c02
	.word	0x11802c02
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	.word	0x11e02c02
	.word	0x11f02c02
	.word	0x12002c02
	.word	0x12102c02
	.word	0x12202c02
	.word	0x12302c02
	.word	0x12402c02
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	.word	0x12602c02
	.word	0x12702c02
	.word	0x12802c02
	.word	0x12902c02
	.word	0x12a02c02
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	.word	0x12e02c02
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	.word	0x13102c02
	.word	0x13202c02
	.word	0x13302c02
	.word	0x13402c02
	.word	0x13502c02
	.word	0x13602c02
	.word	0x13702c02
	.word	0x13802c02
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	.word	0x14802c02
	.word	0x14902c02
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	.word	0x15002c02
	.word	0x15102c02
	.word	0x15202c02
	.word	0x15302c02
	.word	0x15402c02
	.word	0x15502c02
	.word	0x15602c02
	.word	0x15702c02
	.word	0x15802c02
	.word	0x15902c02
	.word	0x15a02c02
	.word	0x15b02c02
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	.word	0x15d02c02
	.word	0x15e02c02
	.word	0x15f02c02
	.word	0x16002c02
	.word	0x16102c02
	.word	0x16202c02
	.word	0x16302c02
	.word	0x16402c02
	.word	0x16502c02
	.word	0x16602c02
	.word	0x16702c02
	.word	0x16802c02
	.word	0x16902c02
	.word	0x16a02c02
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	.word	0x16e02c02
	.word	0x16f02c02
	.word	0x17002c02
	.word	0x17102c02
	.word	0x17202c02
	.word	0x17302c02
	.word	0x17402c02
	.word	0x17502c02
	.word	0x17602c02
	.word	0x17702c02
	.word	0x17802c02
	.word	0x17902c02
	.word	0x17a02c02
	.word	0x17b02c02
	.word	0x17c02c02
	.word	0x17d02c02
	.word	0x17e02c02
	.word	0x17f02c02
	.word	0x18002c02
	.word	0x18102c02
	.word	0x18202c02
	.word	0x18302c02
	.word	0x18402c02
	.word	0x18502c02
	.word	0x18602c02
	.word	0x18702c02
	.word	0x18802c02
	.word	0x18902c02
	.word	0x18a02c02
	.word	0x18b02c02
	.word	0x18c02c02
	.word	0x18d02c02
	.word	0x18e02c02
	.word	0x18f02c02
	.word	0x19002c02
	.word	0x19102c02
	.word	0x19202c02
	.word	0x19302c02
	.word	0x19402c02
	.word	0x19502c02
	.word	0x19602c02
	.word	0x19702c02
	.word	0x19802c02
	.word	0x19902c02
	.word	0x19a02c02
	.word	0x19b02c02
	.word	0x19c02c02
	.word	0x19d02c02
	.word	0x19e02c02
	.word	0x19f02c02
	.word	0x1a002c02
	.word	0x1a102c02
	.word	0x1a202c02
	.word	0x1a302c02
	.word	0x1a402c02
	.word	0x1a502c02
	.word	0x1a602c02
	.word	0x1a702c02
	.word	0x1a802c02
	.word	0x1a902c02
	.word	0x1aa02c02
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	.word	0x1ae02c02
	.word	0x1af02c02
	.word	0x1b002c02
	.word	0x1b102c02
	.word	0x1b202c02
	.word	0x1b302c02
	.word	0x1b402c02
	.word	0x1b502c02
	.word	0x1b602c02
	.word	0x1b702c02
	.word	0x1b802c02
	.word	0x1b902c02
	.word	0x1ba02c02
	.word	0x1bb02c02
	.word	0x1bc02c02
	.word	0x1bd02c02
	.word	0x1be02c02
	.word	0x1bf02c02
	.word	0x1c016caa   @ bcm95301x_svk_iproc_nand_config: make NAND flash code L1&L2 cachable
	.word	0x1c102c02
	.word	0x1c202c02
	.word	0x1c302c02
	.word	0x1c402c02
	.word	0x1c502c02
	.word	0x1c602c02
	.word	0x1c702c02
	.word	0x1c802c02
	.word	0x1c902c02
	.word	0x1ca02c02
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	.word	0x1d002c02
	.word	0x1d102c02
	.word	0x1d202c02
	.word	0x1d302c02
	.word	0x1d402c02
	.word	0x1d502c02
	.word	0x1d602c02
	.word	0x1d702c02
	.word	0x1d802c02
	.word	0x1d902c02
	.word	0x1da02c02
	.word	0x1db02c02
	.word	0x1dc02c02
	.word	0x1dd02c02
	.word	0x1de02c02
	.word	0x1df02c02
	.word	0x1e016caa  @DDR_SHMOO_RELATED_CHANGE: change 0x1e014ca2 to 0x1e016caa to make flash code L1&L2 cachable   
	.word	0x1e104c02
	.word	0x1e204c02
	.word	0x1e304c02
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	.word	0x1e504c02
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	.word	0x1f304c0a
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	.word	0x23e02c02
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	.word	0x24002c02
	.word	0x24102c02
	.word	0x24202c02
	.word	0x24302c02
	.word	0x24402c02
	.word	0x24502c02
	.word	0x24602c02
	.word	0x24702c02
	.word	0x24802c02
	.word	0x24902c02
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	.word	0x25002c02
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	.word	0x25202c02
	.word	0x25302c02
	.word	0x25402c02
	.word	0x25502c02
	.word	0x25602c02
	.word	0x25702c02
	.word	0x25802c02
	.word	0x25902c02
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	.word	0x26002c02
	.word	0x26102c02
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	.word	0xf1f02c02
	.word	0xf2002c02
	.word	0xf2102c02
	.word	0xf2202c02
	.word	0xf2302c02
	.word	0xf2402c02
	.word	0xf2502c02
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	.word	0xf2702c02
	.word	0xf2802c02
	.word	0xf2902c02
	.word	0xf2a02c02
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	.word	0xf2c02c02
	.word	0xf2d02c02
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	.word	0xf2f02c02
	.word	0xf3002c02
	.word	0xf3102c02
	.word	0xf3202c02
	.word	0xf3302c02
	.word	0xf3402c02
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	.word	0xf3602c02
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	.word	0xf3a02c02
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	.word	0xf3d02c02
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	.word	0xf4002c02
	.word	0xf4102c02
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	.word	0xf4402c02
	.word	0xf4502c02
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	.word	0xf6802c02
	.word	0xf6902c02
	.word	0xf6a02c02
	.word	0xf6b02c02
	.word	0xf6c02c02
	.word	0xf6d02c02
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	.word	0xf7502c02
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	.word	0xf8702c02
	.word	0xf8802c02
	.word	0xf8902c02
	.word	0xf8a02c02
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	.text
.globl mmu_table_addr
mmu_table_addr:
	.word mmu_table1
#endif

.globl lowlevel_init
lowlevel_init:
#ifdef CONFIG_DUAL_CORE
    /* Before we do anything, patch the on-SoC vectors */
    /* Note that this may well be happening on both cores at */
    /* the same time. This is not racy as the end result is to */
    /* have a coherent dispatch table */
    LDR	    r0,=0xffff0400		/* Pointer to dispatch table */
    LDR     r1,=0xffff0000		/* Pointer to vectors */
    LDR     r2,=8			/* Set up 8 vectors */
1:
    STR     r1, [r0, #0]		/* Set it up */
    ADD     r0, r0, #4			/* Point to next vector */
    ADD     r1, r1, #4			/* Point to next handler */
    SUB     r2, r2, #1			/* One more done... */
    BNE     1b

    /* If this is the primary CPU, start up U-boot. Secondary */
    /* CPUs return to the holding pen. A secondary CPU should */
    /* only come here once, as the vectors won't get repatched. */

    MRC     p15, 0, r0, c0, c0, 5      /* Identify current CPU */
    AND     r0, r0, #0xf
    CMP     r0, #PRIMARY_CPU
    BEQ     2f
    LDR	    pc,=0xffff0000		/* Back to the SoC holding pen */
2:
#endif
 
#ifdef CONFIG_L2C_AS_RAM
	/* Disable interrupts */
	mrs	r0, cpsr
	orr	r0, r0, #0xc0
	msr	cpsr,r0
	mov r1, #0
	/* Initialize cp15 registers */
    MCR	p15,0,r1,c5,c0,0   /* DFSR */
    MCR	p15,0,r1,c5,c0,1   /* IFSR */
    MCR	p15,0,r1,c6,c0,0   /* DFAR */
    MCR	p15,0,r1,c6,c0,1   /* WFAR */
	
	@ Disable MMU
	MRC p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data
	BIC r1, r1, #0x1
	MCR p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data
	@ Disable L1 Caches
	MRC p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data
	BIC r1, r1, #(0x1 << 12) @ Disable I Cache
	BIC r1, r1, #(0x1 << 2) @ Disable D Cache
	MCR p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data
	@ Invalidate L1 Caches
	@ Invalidate Instruction cache
	MOV r1, #0
	MCR p15, 0, r1, c7, c5, 0

    @ Invalidate BTAC
	MCR p15, 0, r0, c7, c5, 6 	
    mcr p15, 0, r1, c7, c10, 4 /* DSB */
    mcr p15, 0, r0, c7, c5, 4 /* ISB */ 

    @ Enable I cache
    MRC     p15, 0, r0, c1, c0, 0   @ Read Control Register configuration data
    ORR     r0, r0, #(0x3 << 11)    @ Enable I Cache and Branch prediction
    MCR     p15, 0, r0, c1, c0, 0   @ Write Control Register configuration data

    @  Invalidate Data cache
    @ To make the code general purpose, we calculate the cache size first and loop through each set + way
    MOV  r0, #0                  
    MCR  p15 ,2, r0, c0, c0, 0
    mcr p15, 0, r0, c7, c5, 4 /* ISB */ 
    MRC  p15, 1, r0, c0, c0, 0   @  Read Cache Size ID
    LDR  r4, =0x1ff
    AND  r4, r4, r0, LSR #3      @
    ADD  r4, r4, #1              @  r4 = no: of ways
    LDR  r3, =0x7fff
    AND  r0, r3, r0, LSR #13     @  r0 = no. of sets/lines - 1
    ADD  r0, r0, #1              @  r0 = no: of ways
    MOV  r1, #0                  @  r1 = way counter way_loop
way_loop:
    MOV  r3, #0                  @  r3 = set counter set_loop
set_loop:
    MOV  r2, r1, LSL #30 
    ORR  r2, r3, LSL #5          @  r2 = set/way cache operation format
    MCR  p15, 0, r2, c7, c6, 2   @  Invalidate line described by r2
    ADD  r3, r3, #1              @  Increment set counter
    CMP  r0, r3                  @  Last set reached yet?
    BNE  set_loop                @  if not, iterate set_loop
    ADD  r1, r1, #1              @  else, next
    CMP  r1, r4                  @  Last way reached yet?
    BNE  way_loop                @  if not, iterate way_loop

	@ Enable D Cache
    MCR  p15, 0, r1, c7, c10, 4 /* DSB */
    MRC  p15, 0, r0, c1, c0, 0  @ read CP15 register 1 into r0
    ORR  r0, r0, #0x4           @ enable D Cache
    MCR  p15, 0, r0, c1, c0, 0  @ write CP15 register 1
    MCR  p15, 0, r0, c7, c5, 4 /* ISB */ 


	@ Invalidate TLB
	MCR p15, 0, r1, c8, c7, 0	
	@ DSB causes completion of all cache maintenance operations appearing in program
	@ order before the DSB instruction
	@ An ISB instruction causes the effect of all branch predictor maintenance
	@ operations before the ISB instruction to be visible to all instructions
	@ after the ISB instruction.
	/* SCU and L2C inits have to be done only for core-0 */
#ifndef CONFIG_DUAL_CORE
       B scu_enable
#else
       MRC     p15, 0, r0, c0, c0, 5      /* Identify current CPU */
       AND     r0, r0, #0xf
       CMP     r0, #PRIMARY_CPU
       BEQ     scu_enable
       B   mmu_init
#endif
       		
scu_enable:
	/* Invalidate and enable SCU */
    LDR     r0, =IHOST_SCU_INVALIDATE_ALL
    MOV     r1, #0xFF
    STR     r1, [r0]
    LDR     r0, =IHOST_SCU_CONTROL
    LDR     r1, [r0]
    ORR     r1, r1, #0x1
    STR     r1, [r0]

	/* MMU initialization */
mmu_init:    
    /* Configure translation table base (TTB) control register cp15,c2
     to a value of all zeros, indicates we are using TTB register 0 */
    mov     r0,#0x0
    mcr     p15, 0, r0, c2, c0, 2
	/* Load page table address to CP15 */    
	ldr r0, mmu_table_addr
	mcr p15, 0, r0, c2, c0, 0

	/* Set the access control to Client */
	ldr r0, =0x55555555
	mcr p15, 0, r0, c3, c0, 0

	/* Enable MMU */
    MRC p15, 0, r1, c1, c0, 0
    ORR r1, r1, #0x01
    MCR p15, 0, r1, c1, c0, 0
	MCR p15, 0, r0, c7, c5, 4 /* ISB */

	/* SCU and L2C inits have to be done only for core-0 */
#ifndef CONFIG_DUAL_CORE
       B l2cc_init
#else
       MRC     p15, 0, r0, c0, c0, 5      /* Identify current CPU */
       AND     r0, r0, #0xf
       CMP     r0, #PRIMARY_CPU
       BEQ     l2cc_init
       B       coreo_init_done
       
#endif

	/* L2CC Initialization */
l2cc_init:	
	/* read chipID */
	ldr     r0,=0x18000000	/* CHIPID */
	ldr     r1,[r0, #0x0]
	ldr 	r3,=0x0000ffff	/* chipid is bit 0-15 */
	and	r3,r3,r1	/* r3 contains  chipid */

	ldr r0, =IHOST_L2C_CACHE_ID /* L2CC reg base */
	ldr r1, [r0, #0x104]
	bic r1, r1, #0x000F0000 /* Clear the Way-size and associativity (8 way */

	/* check if costar*/
	ldr 	r4, =0xcf19	/* 0xcf19/cf1a/cf1b  - costar; 0xcf12/0xcf13/0xcf14 - ns */
	cmp 	r3,r4
	bge	l2_512_l2cache		
	ldr r2, =0x0A130000  /*0x08150000 ? 0x0A130000*/
	/* northstar */
	b	l2_selection_done		
l2_512_l2cache:
	ldr r2, =0x0A150000  /*0x08150000 ? 0x0A130000*/
	/* costar */
l2_selection_done:
	/* orr r2, r2, #1   *//* Enable full line of write zero */
	orr r1, r1, r2 /* Non-secure interrupt access, Way-size 16KB, 16 way
						    and event monitoring */


    str r1, [r0, #0x104]
#if CONFIG_DEFAULT_L2_CACHE_LATENCY

#else
	/* Set the TAG RAM and DATA RAM latencies for Northstar, skip for co-star */
	cmp 	r3,r4
	bge	skip_l2_latency	 
    ldr r1, =0x0
    str r1, [r0, #0x108]
    ldr r1, =0x0777    
    str r1, [r0, #0x10C]
skip_l2_latency:
#endif
    /* Invalidate the entire L2 cache */
    ldr r1, =0xFFFF
    str r1, [r0, #0x77C] /* inv_way */
    
    mov r2, #0
test_inv_way:    
    ldr r1, [r0, #0x77C]
    cmp r1,r2
    BNE test_inv_way
    
    ldr r1, =0x1FF
    str r1, [r0, #0x220] /* int_clear */
    mov r1, #0x01
    str r1, [r0, #0x100] /* control */
	/* Memory barrier */
	mov r1, #0
	mcr p15, 0, r1, c7, c10, 4 /* DSB */

	/*
	MRC p15, 0, r1, c1, c0, 1 @ Read Auxiliary Control Register
	ORR r1, r1, #(0x1 <<3) @Enable write full line of zero mode
	MCR p15, 0, r1, c1, c0, 1 @ Write Auxiliary Control Register
	*/
	MCR p15, 0, r1, c7, c10, 4 /* DSB */
	MCR p15, 0, r0, c7, c5, 4 /* ISB */

    LDR r1, =0xc0000000
    LDR r2, =0xc0020000
    LDR r4, =0xa5a5a5a5
    LDR r5, =0xa5a5a5a5
    LDR r6, =0xa5a5a5a5
    LDR r7, =0xa5a5a5a5
    LDR r8, =0xa5a5a5a5
    LDR r9, =0xa5a5a5a5
    LDR r10, =0xa5a5a5a5
    LDR r11, =0xa5a5a5a5
    /* Enable lockdown by line */
    mov r3, #0x01
    ldr r0, =IHOST_L2C_CACHE_ID
    str r3, [r0, #0x950]
loop1:
    STMIA r1!, {r4-r11}
    ldr r3, =0x10
cdelay1:
    sub r3, r3, #1
    cmp r3, #0
    bne cdelay1
    cmp r1, r2
    bne loop1
	/* Disable lockdown by line */
    mov r3, #0
    ldr r0, =IHOST_L2C_CACHE_ID
    str r3, [r0, #0x950]		
l2cc_init_done:
#endif
	ldr r0,=ROM_S0_IDM_IO_STATUS  /* get the SKU id */
	ldr	r11,[r0]
	lsr r11,r11, #2 /* Bits [3:2] - strap_sku_vect, 0/3 - HIGH SKU, 1 - Low SKU, 2 - Medium SKU */
	and r11,r11, #3

/* Issue: PCIE slave access is blocked by NIC in Medium SKU */
	cmp r11, #2 /* Check for SKU */
	bne pcie_wa_done 
	/* Medium SKU */
	eor r1,r1,r1 /* r1=0 */
	ldr r0, =AXIIC_REMAP
	str r1, [r0]
	ldr r0, =SDROM_REMAP_SELECT
	str r1, [r0]
	orr r1, r1, #1
	ldr r0, =SDROM_REMAP_SELECT_ENABLE
	str r1, [r0]
pcie_wa_done:

/* Initialize LCPLL to required clocks for DDR */        
lcpll_init:

#ifndef CONFIG_L2C_AS_RAM   /* Do the DDR initialization */
/* DDR initialization */
ddr_init:
        LDR r0, =DDR_S1_IDM_IO_STATUS
        LDR r1, [r0]
	    ANDS r1,r1, #1
	    BEQ ddr3_wa_done 
	    /* DDR3 */
        LDR     r0, =PCU_1V8_1V5_VREGCNTL_OFFSET
        LDR     r1, =0x00000200
        STR     r1, [r0]
        NOP
ddr3_wa_done:	    
        LDR r9, =0x18010000
    	MOV	r8,r9		/* save r9 */

        LDR     r1, =0x18108800
        LDR     r2, =0x00000000
        STR     r2, [r1]
        LDR     r1, =0x18109800
        STR     r2, [r1]
        
        LDR     r1, =0x18108408
        LDR     r2, [r1]
        LDR     r3, =0xf000ffff
        AND     r2, r2, r3
        ORR     r2, r2, #0x01900000
        STR     r2, [r1]

        LDR     r9, =0x18010800
        LDR     r1, =0x0
        LDR     r3, =0x00019000

wait_for_ddr_phy_up:
        CMP     r3, r1
        BEQ     ddr_phy_rdy
        SUB     r3, r3, #0x1
        LDR     r2, =0x0
        LDR     r2, [r9]
        CMP     r2, r1
        BNE     ddr_phy_rdy
        B       wait_for_ddr_phy_up
ddr_phy_rdy:


        LDR     r1, =0x18010814
        LDR     r2, =0x00000010
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r4, =0x18010810
        LDR     r1, =0x1
        LDR     r3, =0x00001400

wait_for_ddr_phy_pll_lock:
        CMP     r3, r1
        BEQ     ddr_phy_pll_lock_done 
        SUB     r3, r3, #0x1
        LDR     r2, =0x0
        LDR     r2, [r4]
        AND     r2, r2, #0x1
        CMP     r2, r1
        BEQ     ddr_phy_pll_lock_done
        B       wait_for_ddr_phy_pll_lock
ddr_phy_pll_lock_done:

        LDR     r1, =0x18010b60
        LDR     r2, =0x00000002
        STR     r2, [r1]
        LDR     r3, [r9]


	/* Write 2 if ddr2, 3 if ddr3 */
        LDR     r1, =0x18108500
        LDR     r3, [r1]
        LDR     r2, =0x00000001
        AND     r3, r2, r3
        ORR     r2, r3, #0x2
        LDR     r1, =0x18010bac
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x1801083c
        LDR     r2, =0x00100000
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010848
        LDR     r2, =0x00000101
        STR     r2, [r1]
        LDR     r3, [r9]
        
        
        LDR     r4, =0x1801084C
        LDR     r1, =0x1
        LDR     r3, =0x00001400


wait_for_ddr_phy_calib_lock:
        CMP     r3, r1
        BEQ     ddr_phy_calib_lock_done 
        SUB     r3, r3, #0x1
        LDR     r2, =0x0
        LDR     r2, [r4]
        AND     r2, r2, #0x1
        CMP     r2, r1
        BEQ     ddr_phy_calib_lock_done
        B       wait_for_ddr_phy_calib_lock
ddr_phy_calib_lock_done:

        
        LDR     r4, =0x1801084C
        LDR     r1, =0x2
        LDR     r2, [r4]
        AND     r2, r2, #0x2
        CMP     r2, r1
        BEQ     ddr_cntrl_prog


calib_override:
        LDR     r1, =0x18010834
        LDR     r2, =0x0001003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a04
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a10
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a14
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a18
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a1c
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a20
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a24
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a28
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a2c
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a30
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010aa4
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010ab0
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010ab4
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010ab8
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010abc
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010ac0
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010ac4
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010ac8
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010acc
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010ad0
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a08
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010a0c
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010aa8
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

        LDR     r1, =0x18010aac
        LDR     r2, =0x0003003f
        STR     r2, [r1]
        LDR     r3, [r9]

ddr_cntrl_prog:
        mov	r9,r8		/* restore r9 */

	ldr	r6,=0x0 /* No sdram params */
	ldr	r5,=0x0
init_regs:
	mov	fp,lr			/* save lr across calls */
	adrl	r0,ddr_init_tab
	bl	ddr_init_regs
	mov	lr,fp			/* restore lr */
	
	/* ddr2 or ddr3 */
	ldr	r8,=0x18108500
	ldr	r0,[r8]
	ldr	r2,=DDR_STAT_DDR3
	and	r0,r0,r2
	cmp	r0,r2
	beq	ddr3_init

ddr2_init:
	mov	fp,lr			/* save lr across calls */
	adrl	r0,ddr2_init_tab
	bl	ddr_init_regs
	mov	lr,fp			/* restore lr */
	b	chparams

ddr3_init:
	mov	fp,lr			/* save lr across calls */
	adrl	r0,ddr3_init_tab
	bl	ddr_init_regs
	mov	lr,fp			/* restore lr */

chparams:
	ldr	r0,=0x0
	cmp	r6,r0
	beq	turnon			/* No sdram params, use default values */

chhalf:
	ldr	r1,=0x80
	and	r1,r1,r6
	cmp	r1,r0
	beq	ch8banks
setreduc:
    ldr r9, =0x18010000
    ldr r1, [r9, #DDRC_CONTROL87]
    ldr	r2,=0x00000100
    orr	r1,r1,r2
    str	r1,[r9,#DDRC_CONTROL87]

ch8banks:
	ldr	r1,=0x40
	and	r1,r1,r6
	cmp	r1,r0
	beq	do4banks
do8banks:
        ldr     r1,[r9,#DDRC_CONTROL82]
        ldr	r2,=~0x00000300
        and	r1,r1,r2
        str	r1,[r9,#DDRC_CONTROL82]
	b	docols
do4banks:
        ldr     r1,[r9,#DDRC_CONTROL82]
        ldr	r2,=~0x00000300
        and	r1,r1,r2
        ldr	r2,=0x00000100
        orr	r1,r1,r2
        str	r1,[r9,#DDRC_CONTROL82]

docols:	
        ldr     r1,[r9,#DDRC_CONTROL82]
        ldr	r2,=~0x07070000
        and	r1,r1,r2
        ldr	r2,=0x700
        and	r2,r2,r6
        lsl	r2,r2,#16
        orr	r1,r1,r2
        str	r1,[r9,#DDRC_CONTROL82]

docaslat:
	ldr	r0,=0x1f
	and	r0,r0,r6		/* cas latency */
	sub	r1,r0,#1		/* wrlat */
	ldr	r2,[r9,#DDRC_CONTROL05]
	ldr	r3,=~0x3f1f3f00
	and	r2,r2,r3
	lsl	r3,r0,#9		/* cas << 9 */
	orr	r2,r2,r3	
	lsl	r3,r0,#25		/* cas << 25 */
	orr	r2,r2,r3
	lsl	r3,r1,#16		/* wrlat << 16 */
	orr	r2,r2,r3
	str	r2,[r9,#DDRC_CONTROL05]
	ldr	r2,[r9,#DDRC_CONTROL06]
	ldr	r3,=~0x0000001f
	and	r2,r2,r3
	orr	r2,r2,r1
	str	r2,[r9,#DDRC_CONTROL06]
	
	ldr	r2,[r9,#DDRC_CONTROL174]
	ldr	r3,=~0x00001f3f
	and	r2,r2,r3
	lsl	r3,r1,#8
	orr	r2,r2,r3
	orr	r2,r2,r1
	str	r2,[r9,#DDRC_CONTROL174]

	ldr	r2,[r9,#DDRC_CONTROL44]
	ldr	r3,=~0x00007000
	and	r2,r2,r3
	mov	r3,r0
	lsl	r3,r3,#12
	orr	r2,r2,r3
	str	r2,[r9,#DDRC_CONTROL44]

	ldr	r2,[r9,#DDRC_CONTROL186]
	ldr	r3,=~0xff000000
	and	r2,r2,r3
	add	r3,r0,#16
	lsl	r3,r3,#24
	orr	r2,r2,r3
	str	r2,[r9,#DDRC_CONTROL186]

	ldr	r8,=0x18108500
	ldr	r3,[r8]
	ldr	r2,=DDR_STAT_DDR3
	and	r3,r3,r2
	cmp	r3,r2
	bne	turnon

	ldr	r2,[r9,#DDRC_CONTROL44]
	ldr	r3,=~0x00007000
	and	r2,r2,r3
	sub	r3,r0,#4
	lsl	r3,r3,#12
	orr	r2,r2,r3
	str	r2,[r9,#DDRC_CONTROL44]
	ldr	r2,[r9,#DDRC_CONTROL45]
	ldr	r3,=~0x00380000
	and	r2,r2,r3
	sub	r3,r0,#6
	lsl	r3,r3,#19
	orr	r2,r2,r3
	str	r2,[r9,#DDRC_CONTROL45]

	ldr	r2,[r9,#DDRC_CONTROL206]
	ldr	r3,=~0x00001f00
	and	r2,r2,r3
	sub	r3,r0,#2
	lsl	r3,r3,#8
	orr	r2,r2,r3
	str	r2,[r9,#DDRC_CONTROL206]

turnon:
	ldr	r0,=DDRC00_START
	ldr	r1,[r9,#DDRC_CONTROL00]
	orr	r1,r1,r0
        str     r1,[r9,#DDRC_CONTROL00]

poll_ddr_ctrl:
        ldr     r0,[r9,#DDRC_CONTROL89]
        ldr     r2,=DDR_INT_INIT_DONE
        and     r0,r2,r0
        cmp     r0,r2
        bne     poll_ddr_ctrl
		
ddr_init_done:
#endif  /* CONFIG_L2C_AS_RAM */     		


/* Setup CCA UART clock divider to 2*/
        LDR     r1, =ChipcommonA_ClkDiv
        LDR     r2, [r1]
        AND     r2, r2, #0xFFFFFF00
        ORR     r2, r2, #0x2 
        STR     r2, [r1]


coreo_init_done:		
#ifdef CONFIG_DUAL_CORE
	MRC     p15, 0, r0, c0, c0, 5      /* Identify current CPU */
        AND     r0, r0, #0xf
        CMP     r0, #PRIMARY_CPU
        BEQ     core0_init_done
         LDR SP, =0xB0FF0000 	
         Bl acpon2ndcore
         B loop2itself
loop2itself:
	B loop2itself	

core0_init_done:
#endif
		mov	pc, lr



#ifndef CONFIG_L2C_AS_RAM   /* DDR init value tables */
ddr_init_regs:
	mov	r2,r0
	ldr	r3,=DDR_TABLE_END
1:	ldr	r4,[r2]
	cmp	r4,r3
	beq	2f
	ldr	r5,[r2,#4]
	lsl	r4,r4,#2
	add	r1,r9,r4
	str	r5,[r1]
	add	r2,r2,#8
	b	1b
2:
	mov	pc,lr

	.align 4
ddr_init_tab:
	.word	14,	0x05051001
	.word	15,	0x000a0a05
	.word	36,	0x01000000
	.word	37,	0x10000000
	.word	38,	0x00100400
	.word	39,	0x00000400
	.word	40,	0x00000100
	.word	42,	0x00000001
	.word	61,	0x00010100
	.word	78,	0x01000200
	.word	79,	0x02000040
	.word	80,	0x00400100
	.word	81,	0x00000200
	.word	83,	0x01ffff0a
	.word	84,	0x01010101
	.word	85,	0x03010101
	.word	86,	0x01000003
	.word	87,	0x0000010c
	.word	88,	0x00010000
	.word	112,	0x00000200
	.word	116,	0x19000000
	.word	117,	0x00000028
	.word	119,	0x00010001
	.word	120,	0x00010001
	.word	121,	0x00010001
	.word	122,	0x00010001
	.word	123,	0x00010001
	.word	130,	0x00000001
	.word	139,	0x00000001
	.word	148,	0xffff0001
	.word	149,	0x00ffff00
	.word	150,	0x0000ffff
	.word	152,	0x03030303
	.word	153,	0x03030303
	.word	156,	0x02006400
	.word	157,	0x02020202
	.word	158,	0x02020202
	.word	160,	0x01020202
	.word	161,	0x01010064
	.word	162,	0x01010101
	.word	163,	0x01010101
	.word	165,	0x00020101
	.word	166,	0x00000064
	.word	168,	0x000a0a00
	.word	170,	0x02000200
	.word	171,	0x02000200
	.word	175,	0x02000200
	.word	176,	0x02000200
	.word	180,	0x80000100
	.word	181,	0x04070303
	.word	182,	0x0000000a
	.word	185,	0x0010ffff
	.word	187,	0x0000000f
	.word	194,	0x00000204
	.word	205,	0x00000040
	.word	DDR_TABLE_END

	.align 4
ddr2_init_tab:
	.word	0,	0x00000400
	.word	3,	0x00000043
	.word	4,	0x000000a7
	.word	5,	0x0a040a02
	.word	6,	0x04020404
	.word	7,	0x05030e14
	.word	8,	0x030e1404
	.word	9,	0x04020305
	.word	10,	0x03005b26
	.word	11,	0x04020303
	.word	12,	0x03005b26
	.word	13,	0x01000003
	.word	16,	0x030000c8
	.word	17,	0x00860000
	.word	18,	0x05050086
	.word	20,	0x00002301
	.word	21,	0x00230a24
	.word	22,	0x00050a24
	.word	23,	0x00000200
	.word	24,	0x000a0002
	.word	25,	0x0002000a
	.word	26,	0x00020008
	.word	27,	0x00c80008
	.word	28,	0x00c80027
	.word	29,	0x00000027
	.word	30,	0x03000001
	.word	31,	0x00030303
	.word	44,	0x00085300
	.word	45,	0x00000004
	.word	46,	0x00040853
	.word	48,	0x08530000
	.word	49,	0x00000004
	.word	50,	0x00040853
	.word	52,	0x08530000
	.word	53,	0x00000004
	.word	54,	0x00040853
	.word	56,	0x08530000
	.word	57,	0x00000004
	.word	58,	0x00040853
	.word	82,	0x01030101
	.word	108,	0x02020101
	.word	109,	0x08080404
	.word	110,	0x03020200
	.word	111,	0x01000202
	.word	128,	0x001d1d00
	.word	129,	0x1d1d0001
	.word	133,	0x00011d1d
	.word	134,	0x00011d1d
	.word	137,	0x001d1d00
	.word	138,	0x1d1d0001
	.word	142,	0x00011d1d
	.word	143,	0x00011d1d
	.word	146,	0x001d1d00
	.word	147,	0x1d1d0001
	.word	169,	0x0a240000
	.word	172,	0x00000a24
	.word	173,	0x000032b4
	.word	174,	0x0a240404
	.word	177,	0x00000a24
	.word	178,	0x000032b4
	.word	179,	0x02020404
	.word	186,	0x15070303
	.word	202,	0x0001046b
	.word	203,	0x0001046b
	.word	206,	0x01030301
	.word	207,	0x00000001
	.word	DDR_TABLE_END

	.align 4
ddr3_init_tab:
	.word	0,	0x00000600
	.word	3,	0x0001046b
	.word	4,	0x00028b0b
	.word	5,	0x0c050c00
	.word	6,	0x04040405
	.word	7,	0x05040e14
	.word	8,	0x040e1404
	.word	9,	0x0c040405
	.word	10,	0x03005b68
	.word	11,	0x0c040404
	.word	12,	0x03005b68
	.word	13,	0x01000004
	.word	16,	0x03000200
	.word	17,	0x00000f0f
	.word	18,	0x05050000
	.word	20,	0x00007801
	.word	21,	0x00780a20
	.word	22,	0x00050a20
	.word	23,	0x00000300
	.word	24,	0x000a0003
	.word	25,	0x0000000a
	.word	27,	0x02000000
	.word	28,	0x0200005a
	.word	29,	0x0000005a
	.word	30,	0x05000001
	.word	31,	0x00050505
	.word	44,	0x00022000
	.word	45,	0x00000046
	.word	46,	0x00460210
	.word	48,	0x02100000
	.word	49,	0x00000046
	.word	50,	0x00460210
	.word	52,	0x02100000
	.word	53,	0x00000046
	.word	54,	0x00460210
	.word	56,	0x02100000
	.word	57,	0x00000046
	.word	58,	0x00460210
	.word	82,	0x01010001
	.word	108,	0x02040108
	.word	109,	0x08010402
	.word	110,	0x02020202
	.word	111,	0x01000201
	.word	128,	0x00212100
	.word	129,	0x21210001
	.word	133,	0x00012121
	.word	134,	0x00012121
	.word	137,	0x00212100
	.word	138,	0x21210001
	.word	142,	0x00012121
	.word	143,	0x00012121
	.word	146,	0x00212100
	.word	147,	0x21210001
	.word	169,	0x0a200000
	.word	172,	0x00000a20
	.word	173,	0x000032a0
	.word	174,	0x0a200505
	.word	177,	0x00000a20
	.word	178,	0x000032a0
	.word	179,	0x02020505
	.word	186,	0x16070303
	.word	202,	0x00000004
	.word	203,	0x00000004
	.word	206,	0x01040401
	.word	207,	0x00000001
	.word	DDR_TABLE_END
#endif /* CONFIG_L2C_AS_RAM */
